Logic device/transceiver/encoder

Single 2-Input, 0.8V to 2.7V High Speed ​​NAND Gate 5-DSBGA -40 to 85

4-Channel, 2-Input, 1.65V to 3.6V OR Gate 14-SO -40 to 85

4-Channel, 4-Input, 4.5V to 5.5V NAND Gate with Schmitt Trigger Inputs 14-SO -40 to 85

4-Channel, 2-Input, 2V to 6V NAND Gate 14-SOIC -55 to 125

Automotive 4-Channel, 2-Input, 2V to 6V AND Gate 14-TSSOP -40 to 125

Automotive super configurable multifunction gate with 3-state outputs 8-VSSOP -40 to 125

The MC14099B and MC14599B are 8-bit addressable latches. Data is clocked in serially when the corresponding latch is addressed (via address pins A0, A1, A2) and write disable is low. Chip Enable must be high to write to the MC14599B. For the MC14599B, ​​the data pin is a bidirectional data port; for the MC14099B, the input is a unidirectional write-only port. The write/read lines control this port in the MC14599B. Data is presented in parallel on the 8 latched outputs, independent of the state of write-disable, write/read, or chip-enable. Both components have a master reset function.