Logic device/transceiver/encoder

The MC14018B contains five Johnson counter stages that can be preset and reset asynchronously. These counters are synchronous and increment on the rising edge of the clock. Presetting is accomplished with a logic 1 on the Preset Enable input. Data on the Jam inputs will then be transferred to their respective Qbar outputs (inverted). A logic 1 on the reset input will put all Qbar outputs into a logic 1 state. A divide by 2 to 10 can be accomplished by connecting the appropriate Qbar output to the data input as shown in the function selection table. The MC14018B includes an anti-lock gate to ensure correct counting sequence.

High Speed ​​CMOS Logic Presettable Synchronous BCD Decimal Up/Down Counter 16-SO -55 to 125

High Speed ​​CMOS Logic 4-Bit Parallel Access Register 16-SOIC -55 to 125

The NC7S02 is a single channel 2-input high performance CMOS NOR gate. Advanced silicon-gate CMOS fabrication techniques ensure wide V