RTC clock synchronization buffer driver delay chip

Programmable 3-PLL VCXO Clock Synthesizer with 1.8V LVCMOS Output 20-TSSOP -40 to 85

The MC100LVEL14 is a low-skew 1:5 distribution chip specifically designed for low-skew clock distribution applications. The device can be driven by differential or single-ended ECL, or by a PECL input signal if a positive supply is used. The LVEL14 is functionally and pin compatible with the EL14 implementation, but is designed to operate in ECL or PECL with a voltage supply range of -3.0 V to -3.8 V (or 3.0 V to 3.8 V). The LVEL14 has a multiplexed clock input that can be used to distribute lower speed scan or test clocks as well as high speed system clocks. When LOW (or left open and pulled LOW by an input pull-down resistor), the SEL pin selects the differential clock input. The common enable (EN) is synchronous, so the output is only enabled/disabled when it is in the low state. This avoids short clock pulses when devices are enabled/disabled, which can happen in asynchronous control. The internal flip-flops are clocked on the falling edge of the input clock, so all relevant specification limits are referenced to the negative edge of the clock input. Only the VBB pin, the internally generated supply voltage, is provided for this device. In the case of single-ended inputs, tie the unused differential input to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC with 0.01 5F capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use.

CDCLVP1212 Low Jitter 2 Input Selectable 1:12 General Purpose LVPECL Buffer