RTC clock synchronization buffer driver delay chip

The MC100LVEP210 is a low skew 1:5 dual differential driver designed with clock distribution in mind. The ECL/PECL input signal can be differential or single-ended if the VBB output is used. Signals are fanned out to 5 identical differential outputs. The HSTL input can be used when the EP210 is running in PECL mode. The LVEP210 specifically guarantees low output-to-output skew. Optimized design, layout, and handling minimize skew within and between devices. To ensure tight skew specifications are met, both ends of the differential output need to be equally terminated to 50Ω even if only one output is used. If the output pair is not used, both outputs can be left open (unterminated) without affecting the skew ratio. Like most other ECL devices, the MC100LVEP210 can be powered from a positive VCC supply in PECL mode. Therefore, using the LVEP210 in +3.3 V or +2.5 V systems enables high performance clock distribution. Single-ended CLK input operation is limited to VCC ≤ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode. Designers can take advantage of the performance of the LVEP210 to distribute low-skew clocks on a backplane or motherboard. In a PECL environment, serial or Thevenin line terminations are often used because they do not require an additional power supply. For more information on using PECL, designers should refer to application note AN1406/D.

156.25MHz, ±25ppm, LVPECL Ultra-Low Jitter Standard Differential Oscillator 6-QFM -40 to 85