RTC clock synchronization buffer driver delay chip

The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. The input MUX selects one of two LVCMOS/LVTTL CLK lines by using the CLK_SEL pin of the LVCMOS/LVTTL level (CLK1 is high, CLK0 is low). The CLK_EN pin can synchronously enable or disable the output using LVCMOS/LVTTL levels (high level enables the output, low level disables the output) to eliminate short pulses.