RTC clock synchronization buffer driver delay chip

The MC100EP140 is a 3-state phase-frequency detector for phase-locked loop applications that require minimal phase and frequency difference when locking. Due to the fully differential gate design of the part, the overall circuit noise is reduced, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to "compare" an input signal (feedback) with a set reference signal. When the frequency and/or phase of the reference (R) and feedback (FB) inputs are different, the differential UP (U) and DOWN (D) outputs provide pulse streams that, if subtracted and integrated, provide the control VCO the error voltage. The device is packaged in a small surface-mount 8-lead SOIC package. The EP140's output is 400 mV, allowing for faster switching times and greater bandwidth. The device can also be used in +3.3 V systems. For proper operation, the input edge rate on the R and FB inputs should be less than 5 ns. See AND8040 for more information on Phase Locked Loop operation and applications.